65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application
This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%. authors: S.K.H. Fung, H.T. Huang, S.M. Cheng, K.L. Cheng, S.W. Wang, Y.P. Wang, Y.Y. Yao, C.M. Chu, S.J. Yang, W.J. Liang, Y.K. Leung, C.C. Wu, C.Y. Lin, S.J. Chang, S.Y. Wu, C.F. Nieh, C.C. Chen, T.L. Lee, Y. Jin, S.C. Chen, L.T. Lin, Y.H. Chiu, H.J. Tao, C.Y. Fu, S.M. Jang, K.F. Yu, C.H. Wang, T.C. Ong, Y.C. See, C.H. Diaz
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
