Improvement of ultra-thin gate oxide by a novel rapid thermal oxidation process with in-situ steam generation
This paper reports for the first time the growth of ultra- thin gate oxide by rapid thermal oxidation using in-situ generated steam (Wet RTO). Compared to conventional gate oxide grown by wet furnace and dry RTO, excellent oxide integrity of Wet RTO is demonstrated. Furthermore, the Wet RTO oxides nitrided by in-situ NO rapid thermal anneal also exhibits improved device transconductance, current drivability, and hot carrier reliability. authors: Mo-Chium Yu, Syun-Ming Jang, C. H. Diaz, C. H. Yu, S. C. Sun, M. S. Liang
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
