Enabling Multiple-Vt Device Scaling for CMOS Technology beyond 7nm Node
For the first time, multiple-Vt (multi-Vt) device options with Vt range> 250 mV are achieved in standard cells at dimensions beyond 7nm technology node. To overcome the common scaling challenges of potential device options such as FinFET and gate all-around (GAA) nanosheet transistor - gate length and cell height scaling, key enablers are identified, including novel, thin, and conformal work function metal (WFM) with enhanced patterning efficiency, high-k (HK) engineering, and precise WFM patterning boundary control. This work enables design flexibility for advanced CMOS technology beyond 7nm node with critical differentiators. authors: Vincent S. Chang, S. H. Wang, J. H. Lu, W. H. Wu, B. F. Wu, B. C. Hsu, K. C. Kwong, J. Y. Yeh, C. H. Chang, C. H. Chen, C. O. Chui, M. S. Yeh, K. B. Huang, R. Chen, K. S. Chen, S. Y. Wu
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
