Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs
We demonstrated that FinFET CMOS logic technologies are capable of ~50% speed increase at constant operating power when operating at 77K, or 0.27× power reduction at constant speed. The benefits arise primarily from steeper SS, carrier transport enhancement, and lower interconnect resistances. Better reliability enables additional speed gain for single-thread computing to ~70%. To extract this benefit, gate work function engineering at the transistor level is necessary. And design technology co-optimization at system level can further bring additional benefits. authors: H. L. Chiang, T. C. Chen, J. F. Wang, S. Mukhopadhyay, W. K. Lee, C. L. Chen, W. S. Khwa, B. Pulicherla, P. J. Liao, K. W. Su, K. F. Yu, T. Wang, H. S. P. Wong, C. H. Diaz, J. Cai
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
