CMOS-Compatible GaN-on-Si Field-Effect Transistors for High Voltage Power Applications
CMOS-compatible 100/650 V enhancement-mode FETs and 650 V depletion-mode MISFETs are fabricated on 6-inch AlGaN/GaN-on-Si wafers. They show high breakdown voltage and low specific on-resistance with good wafer uniformity. The importance of epitaxial quality is figured out in a key industrial item: high-temperature-reverse-bias-stress-induced on-state drain curent degradation. Optimization of epitaxial layers shows significant improvement of device reliability. authors: Man Ho Kwan, K.-Y. Wong, Y. S. Lin, F.W. Yao, M. W. Tsai, Y.-C. Chang, P. C. Chen, R.Y. Su, C.-H. Wu, J. L. Yu, F. J. Yang, G. P. Lansbergen, H.-Y. Wu, M.-C. Lin, C. B. Wu, Y.-A. Lai, C.-W. Hsiung, P.-C. Liu, H.-C. Chiu, C.-M. Chen, C. Y. Yu, H. S. Lin, M.-H. Chang, S.-P. Wang, L. C. Chen, J. L. Tsai, H.C. Tuan, Alex Kalnitsky
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
