28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications
An industry leading 28nm high-performance mobile SoC technology featuring metal-gate/high-k process is presented. The technology is optimized to offer wide power-to-performance transistor dynamic range and highest wired gate density with superior low-R/ELK interconnects, critical for next generation mobile computing/SOC applications. Through process and design optimization, historical trend is maintained for gate density and SRAM cell sizes. Variations control strategy through process and design collaboration is also described. authors: S.H. Yang, J.Y. Sheu, M.K. Ieong, M.H. Chiang, T. Yamamoto, J.J. Liaw, S.S. Chang, Y.M. Lin, T.L. Hsu, J.R. Hwang, J.K. Ting, C.H. Wu, K.C. Ting, F.C. Yang, C.M. Liu, I.L. Wu, Y.M. Chen, S.J. Chent, K.S. Chen, J.Y. Cheng, M.H Tsai, W. Chang, R. Chen, C.C. Chen, T.L. Lee, C.K Lin, S.C. Yang, Y.M. Sheu, J.T. Tzeng, L.C. Lu
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
