ALT Highlight: First Demonstration of Monolithic CFET Inverter at 48nm Gate Pitch Toward Future Logic Technology Scaling
This study presents the first functional advanced CFET inverter with an industry-leading 48nm gate pitch, exhibiting well-balanced voltage transfer characteristics up to 1.2 V. In this paper, we elaborate on the advancements in our nanosheet-based monolithic complementary field-effect transistor (mCFET) process architecture, which builds upon our previous work. Key developments include a vertical dipole patterning process for independent n/p threshold voltage tuning, a vertical metallized drain local interconnect for n/p epitaxy connection at the common drain, and backside middle-of-line contacts and interconnects that improve performance and increase design flexibility. A comprehensive evaluation of the electrical performance of the mCFET devices with different configurations validates the effectiveness of our integrated process architecture. The successful demonstration of fully operational mCFET inverters marks an important milestone in the pioneering of CFET technology, paving the way for future logic technology scaling and the advancement of power, performance, area, and cost (PPAC). authors: Szuya Liao, Lu Yang, Wei-Xiang You, Ting-Yun Wu, Yi-Che Lee, Tsung-Kai Chiu, James Hsu, Wei-Der Ho, Yuan-Chi Yang, Ming-Chang Tsai, Hsin Yang Hun, Rui-FU Chen, Yi-Hsuan Li, Shao-Tse Huang, Ching Yen Lee, Ku-Feng Yang, Kuan-Kan Hu, Yu-Hsien Chiang, Hung-Kun Lo, Shih-Jung Ho, Chu-Hsuan Sha, Jin-Hao Jhang, Guan-Ren Wang, Chun-Yu Liu, Wei-Yen Woon, Cheng-Ming Lin, Szu-Hua Chen, Kai-Chieh Yang, Je-Ruei Wen, Chia-Min Chang, Yu-Tien Shen, Pinyen Lin, Chi-Ming Yang, Wei-Yip Loh, Gene Tsai, Chih Hung Chen, Richard Chen, Min Cao
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
