A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications
A leading edge 90nm bulk CMOS device technology is described in this paper. In this technology, multi Vt and multi gate oxide devices are offered to support low standby power (LP), general-purpose (G or ASIC), and high-speed (HS) system on chip (SoC) applications. High voltage I/O devices are supported using 70/spl Aring/, 50/spl Aring/, and 28/spl Aring/ gate oxide for 3.3V, 2.5V, and 1.5-1.8V interfaces, respectively. The backend architecture is based on nine levels of Cu interconnect with hot black diamond (HBD) low-k dielectric (k<=3.0). authors: C.C. Wu, Y.K. Leung, C.S. Chang, M.H. Tsai, H.T. Huang, D.W. Lin, Y.M. Sheu, C.H. Hsieh, W.J. Liang, L.K. Han, W.M. Chen, S.Z. Chang, S.Y. Wu, S.S. Lin, H.C. Lin, C.H. Wang, P.W. Wang, T.L. Lee, C.Y. Fu, C.W. Chang, S.C. Chen, S.M. Jang, S.L. Shue, H.T. Lin, Y.C. See, Y.J. Mii, C.H. Diaz, B.J. Lin, M.S. Liang, Y.C. Sun
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
