A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications
A leading-edge 0.13 /spl mu/m CMOS technology using 193 nm lithography and Cu/low-k interconnect is described in this paper. High performance 80 nm core devices use 17 /spl Aring/ nitrided oxide for 1.0-1.2 V operation. These devices deliver unloaded 8.5 ps gate delay @1.2 V. This technology also supports general ASIC applications with 20 /spl Aring/ oxide for 1.2-1.5 V operation and low-standby power applications with 26 /spl Aring/ for 1.5 V operation, respectively. Dual gate oxides of 50 or 65 /spl Aring/ are also supported for 2.5 V or 3.3 V I/O circuits respectively. Cu with low-k dielectric is used for the 8-layer metal interconnect system with tight pitch. The aggressive design rules and border-less contacts/vias support a high density 1P3M 2.43 /spl mu/m/sup 2/ 6T-SRAM cell without local interconnect. A suite of embedded SRAM cells (6T, 8T) with competitive density and performance optimized for different applications are also supported with memory compilers and large block macros. authors: K.K. Young, S.Y. Wu, C.C. Wu, C.H. Wang, C.T. Lin, J.Y. Cheng, M. Chiang, S.H. Chen, T.C. Lo, Y.S. Chen, J.H. Chen, L.J. Chen, S.Y. Hou, J.J. Law, T.E. Chang, C.S. Hou, J. Shih, S.M. Jeng, H.C. Hsieh, Y. Ku, T. Yen, H. Tao, L.C. Chao, S. Shue, S.M. Jang, T.C. Ong, C.H. Yu, M.S. Liang, C.H. Diaz, J.Y.C. Sun
Logic
Transistor Structure
TSMC CMOS logic technology relied on planar transistor structures until 2014, when FinFETs were introduced into production with our 16nm technology. The FinFET structure resolved a fundamental limitation of planar device scaling, namely the poor electrostatic control of the channel at short gate lengths. FinFETs also enabled a partial decoupling of the transistor density scaling from device effective width scaling, which is an important feature for attaining increased transistor current per unit footprint of transistors. These FinFET characteristics enabled significant reduction of the power supply voltage as compared to planar transistors. FinFET also presents new degrees of freedom for power performance optimization, which contributed to significant enhancements in energy efficiency from 16nm to our most recently introduced 5nm technology node.
TSMC research and development continues to explore next-generation structures such as stacked nanowires or stacked nanosheets in our quest for new heights in computing performance and energy efficiency for future technology nodes.
