Advance Patterning Approach for Cu/Low-k interconnects
The RC delay, electro migration (EM) and TDDB performance become more challenges to meet device requirement as continuous geometry shrink on BEOL dual damascene interconnects. To overcome these challenges from interconnect patterning point of view, we proposed Cu subtractive RIE as a potential solution for next generation Cu/Low-k interconnects. authors: C. H. Tsai, C. J. Lee, C. H. Huang, Jay Wu, H. W. Tien, H. C. Yao, Y. C. Wang, S. L. Shue, M. Cao
Interconnect
On-chip Interconnect
On-chip interconnect today is based on copper/low-k wiring – in today’s chips, there can be more than 100 km of copper wires.
TSMC’s leading edge technologies use a novel copper gap-fill solution to enable the fabrication of smaller conductor lines. Newly-developed materials and processes allow significant reduction in line and via resistance to improve chip performance. A comprehensive suite of innovations on integration scheme, low-k material, and low-k process with selective deposition further enhance both performance (through capacitance reduction) and reliability. Beyond copper interconnect, explorations of single metallic elements, binary and ternary alloys, and 2D materials for future interconnect materials are underway both within TSMC and with our academic partners.
