Low-via-resistance and low-cost PVD-TiZrN barrier for Cu/low-K interconnects
In this work, a low-resistance and low-cost PVD-TiZrN barrier is evaluated for BEOL interconnect. Comparing to conventional PVD barrier, comparable Cu barrier and Cu wetting properties are obtained. Moreover, up to 55% of via resistance reduction is achieved, with comparable voltage breakdown performance comparing to conventional one. authors: Yu-Chen Chan, Chao-Hsien Peng, Ming-Han Lee, Shin-Yi Yang, Ching-Fu Yeh, Shau-Lin Shue
Interconnect
On-chip Interconnect
On-chip interconnect today is based on copper/low-k wiring – in today’s chips, there can be more than 100 km of copper wires.
TSMC’s leading edge technologies use a novel copper gap-fill solution to enable the fabrication of smaller conductor lines. Newly-developed materials and processes allow significant reduction in line and via resistance to improve chip performance. A comprehensive suite of innovations on integration scheme, low-k material, and low-k process with selective deposition further enhance both performance (through capacitance reduction) and reliability. Beyond copper interconnect, explorations of single metallic elements, binary and ternary alloys, and 2D materials for future interconnect materials are underway both within TSMC and with our academic partners.
