High performance/reliability Cu interconnect with selective CoWP cap
In this work, a selective CoWP metal cap was employed after Cu CMP process for replacing conventional dielectric cap layer platform. A 5% reduction in RC delay was demonstrated for this new approach. The CoWP cap layer improves the interface between Cu and dielectric layer which reduces the Cu surface migration. EM for both via and trench shows more than 10X improvement. With optimized thickness and deposited process, 100% yield of line to line leakages, via chain Rc, and metal line Rs can be achieved. A semi-quantitative model was employed to determine surface migration dominating EM failure. authors: T. Ko, C.L. Chang, S.W. Chou, M.W. Lin, C.J. Lin, C.H. Shih, H.W. Su, M.H. Tsai, W.S. Shue, M.S. Liang
Interconnect
On-chip Interconnect
On-chip interconnect today is based on copper/low-k wiring – in today’s chips, there can be more than 100 km of copper wires.
TSMC’s leading edge technologies use a novel copper gap-fill solution to enable the fabrication of smaller conductor lines. Newly-developed materials and processes allow significant reduction in line and via resistance to improve chip performance. A comprehensive suite of innovations on integration scheme, low-k material, and low-k process with selective deposition further enhance both performance (through capacitance reduction) and reliability. Beyond copper interconnect, explorations of single metallic elements, binary and ternary alloys, and 2D materials for future interconnect materials are underway both within TSMC and with our academic partners.
