Advanced System Integration for High Performance Computing with Liquid Cooling
5G and AI technologies are widely applied to highly connected world across cloud, network and edge applications. The compute and bandwidth of high performance computing (HPC) systems such as supercomputer, data center and high-end servers are constantly upgraded to fulfill the ever-increasing challenge from data analytic workload on massive and complicated data. As such, the thermal dissipation issue becomes more of a concern when advanced technology node logic processor operates at high frequency, in particular co-packages with high bandwidth memory (HBM). In this study, we present an industry first advanced liquid cooling technology for HPC on a CoWoS (Chip on Wafer on Substrate) with thermal design power (TDP) up to 2KW. The measurement results show the junction-to-ambient thermal resistance θJA is about 0.064 (°C/W) for lidded liquid cooling with thermal interface material (TIM) and 0.055 (°C/W) for direct liquid cooling at a flow rate of 40 ml/s. A finite element analysis model is further applied to find out the influence of key parameters on the heat dissipation performance. authors: Jeng-Nan Hung, Hung-Chi Li, Po-Fan Lin, Terry Ku, C. H. Yu, KC Yee, Douglas C. H. Yu
Interconnect
Off-chip Interconnect
Silicon interposer, high-density fine-pitch fan-out RDL and bumpless bond are the three pillars of chip-to-chip interconnect on innovative advanced heterogeneous integration technologies (HIT). Each interconnect technology provides the best PPACC in their own domains of AI and 5G networks, and is tightly associated with a wafer-level heterogeneous integration technology, namely CoWoS, InFO and SoIC, respectively, in HPC and mobile application systems.
TSMC’s off-chip interconnect technologies continues to advance for better PPACC:
- Silicon interposer: high interconnect density, high specific capacitance density, and large reticle size for exascale HPC/AI
- Fan-out: high interconnect density and large reticle size in fan-out for cost and performance in HPC/network AI
- SoIC: high 3D interconnect density with ultra-low bonding latency for energy efficient computing systems
Note: PPACC: Power consumption, Performance, Area (form factor), Cost, Cycle time to market
