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Off-chip Interconnect

Silicon interposer, high-density fine-pitch fan-out RDL and bumpless bond are the three pillars of chip-to-chip interconnect on innovative advanced heterogeneous integration technologies (HIT). Each interconnect technology provides the best PPACC in their own domains of AI and 5G networks, and is tightly associated with a wafer-level heterogeneous integration technology, namely CoWoS, InFO and SoIC, respectively, in HPC and mobile application systems.

TSMC’s off-chip interconnect technologies continues to advance for better PPACC:

  1. Silicon interposer: high interconnect density, high specific capacitance density, and large reticle size for exascale HPC/AI
  2. Fan-out: high interconnect density and large reticle size in fan-out for cost and performance in HPC/network AI
  3. SoIC: high 3D interconnect density with ultra-low bonding latency for energy efficient computing systems

Note: PPACC: Power consumption, Performance, Area (form factor), Cost, Cycle time to market

  • InFO (Wafer Level Integrated Fan-Out) Technology

    2016
    A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices. This novel InFO technology is the first high performance Fan-Out Wafer Level Package (FO_WLP) with multi-layer high density interconnects proposed to the industry. In this paper we present the detailed comparison of InFO packages on package (InFO_PoP) with several other previously proposed 3D package solutions. Result shows that InFO_PoP has more optimized overall results on system performance, leakage power and area (form factor) than others, to meet the ever-increasing system requirements of mobile computing. InFO technology has been successfully qualified on package level with robust component and board level reliability. It is also qualified at interconnect level with high electromigration resistance. With its high flexibility and strong capability of multi-chips integration for both homogeneous and heterogeneous sub-systems, InFO technology not only provides a system scaling solution but also complements the chip scaling and helps to sustain the Moore's Law for the smart mobile as well as internet of things (IoT) applications. authors: Chien-Fu Tseng, Chung-Shi Liu, Chi-Hsi Wu, Douglas Yu