Fracture Modeling and Characterization of Underfill/Polymer Interfacial Adhesion in RDL Interposer Package
In order to ensure good performance and long-term reliability of fan-out package, the interfacial strength of Underfill (UF) and polymer (PM) lamination plays an important role because of physical strength and electrical requirement. Accordingly, the present study presents a combined experimental and finite element modeling approach for quantitatively determining the interfacial adhesive strength of UF-PM structures. In the proposed approach, four points bending (FPB) testing is used to evaluate the adhesion strength between UF-PM. The test results are used to determine the critical strain energy release rate (Gc) at the UF-PM interface. The experimental results are then taken as a reference for finite element (FE) simulations. The virtual crack closure technique (VCCT) in FE model is introduced here for risk assessment such as delamination or crack risk at the interface of UF-PM. In general, the results confirm that the proposed predictive modeling approach provides an effective means of evaluating the delamination risk in UF-PM systems. As such, it provides a convenient and cost-effective method for evaluating the new material interface of UF-PM. authors: Shu-Shen Yeh, P. Y. Lin, C. K. Hsu, Y. S. Lin, J. H. Wang, P. C. Lai, C. H. Chen, Y. C. Lee, M. C. Yew, S. K. Cheng, Shin-Puu Jeng
Interconnect
Off-chip Interconnect
Silicon interposer, high-density fine-pitch fan-out RDL and bumpless bond are the three pillars of chip-to-chip interconnect on innovative advanced heterogeneous integration technologies (HIT). Each interconnect technology provides the best PPACC in their own domains of AI and 5G networks, and is tightly associated with a wafer-level heterogeneous integration technology, namely CoWoS, InFO and SoIC, respectively, in HPC and mobile application systems.
TSMC’s off-chip interconnect technologies continues to advance for better PPACC:
- Silicon interposer: high interconnect density, high specific capacitance density, and large reticle size for exascale HPC/AI
- Fan-out: high interconnect density and large reticle size in fan-out for cost and performance in HPC/network AI
- SoIC: high 3D interconnect density with ultra-low bonding latency for energy efficient computing systems
Note: PPACC: Power consumption, Performance, Area (form factor), Cost, Cycle time to market
