Off-chip Interconnect

Silicon interposer, high-density fine-pitch fan-out RDL and bumpless bond are the three pillars of chip-to-chip interconnect on innovative advanced heterogeneous integration technologies (HIT). Each interconnect technology provides the best PPACC in their own domains of AI and 5G networks, and is tightly associated with a wafer-level heterogeneous integration technology, namely CoWoS, InFO and SoIC, respectively, in HPC and mobile application systems.

TSMC’s off-chip interconnect technologies continues to advance for better PPACC:

  1. Silicon interposer: high interconnect density, high specific capacitance density, and large reticle size for exascale HPC/AI
  2. Fan-out: high interconnect density and large reticle size in fan-out for cost and performance in HPC/network AI
  3. SoIC: high 3D interconnect density with ultra-low bonding latency for energy efficient computing systems

Note: PPACC: Power consumption, Performance, Area (form factor), Cost, Cycle time to market

  • Heterogeneous Integration of a Compact Universal Photonic Engine for Silicon Photonics Applications in HPC

    One of the prominent challenges for widespread adoption of Si photonics (SiPh) technology is the availability of an integration platform that can simultaneously meet a wide range of power, performance, and cost criteria in different applications. As a result, there is a diversity of Si photonics integrated solutions proposed or demonstrated, but none is considered as a common solution. In this paper, we will first survey industry proposed photonic engine (PE) structures in monolithic, 2D, 2.5D, and 3D on their strengths and weaknesses. We will then propose a compact and universal PE structure- COUPE (COmpact Universal Photonic Engine) that could consolidate different requirements onto the same integration platform. COUPE has the EIC-PIC integration with the electrical interface designed to minimize the EIC-PIC coupling loss. Compared with industry proposed PE technology, COUPE can provide low insertion loss for both grating coupler (GC) and edge coupler (EC). For either GC or EC, the COUPE is a solid structure without cavities or mechanically weak parts, thus enabling low insertion loss without contamination or mechanical concerns. COUPE also has the flexibility to be integrated easily with host ASIC to form a co-package structure. The COUPE integration scheme can meet the most demanding system requirements and pave the way for silicon photonics based wafer level system integration (WLSI) for high performance computing (HPC) applications. authors: Hsing-Kuo Hsia, C.H. Tsai, K.C. Ting, F.W. Kuo, C.C. Lin, C.T. Wang, S.Y. Hou, W.C. Chiou, Douglas C. H. Yu