Array Antenna Integrated Fan-out Wafer Level Packaging (InFO-WLP) for Millimeter Wave System Applications
Array antenna integrated with RF chip using InFO-WLP technology is proposed for millimeter wave system applications. Aperture-coupled patch antenna is designed on the fan-out molding compound (MC). The performance of single-element antenna is evaluated first and proved to have 5 dBi of gain. Meanwhile, the interconnect from chip to antenna feeding line is demonstrated to only have 0.7 dB loss, which can save 19 % PA output power compared with that of flip-chip package. Finally, the system performance of 4 × 4 antenna array integrated with RF chip on the InFO structure shows 14.7 dBi of array gain in a small form factor of 10 × 10 × 0.5 mm 3 . authors: Chung-Hao Tsai, Jeng-Shien Hsieh, Monsen Liu, En-Hsiang Yeh, Hsu-Hsien Chen, Ching-Wen Hsiao, Chen-Shien Chen, Chung-Shi Liu, Mirng-Ji Lii, Chuei-Tang Wang, Doug Yu
Interconnect
Off-chip Interconnect
Silicon interposer, high-density fine-pitch fan-out RDL and bumpless bond are the three pillars of chip-to-chip interconnect on innovative advanced heterogeneous integration technologies (HIT). Each interconnect technology provides the best PPACC in their own domains of AI and 5G networks, and is tightly associated with a wafer-level heterogeneous integration technology, namely CoWoS, InFO and SoIC, respectively, in HPC and mobile application systems.
TSMC’s off-chip interconnect technologies continues to advance for better PPACC:
- Silicon interposer: high interconnect density, high specific capacitance density, and large reticle size for exascale HPC/AI
- Fan-out: high interconnect density and large reticle size in fan-out for cost and performance in HPC/network AI
- SoIC: high 3D interconnect density with ultra-low bonding latency for energy efficient computing systems
Note: PPACC: Power consumption, Performance, Area (form factor), Cost, Cycle time to market
