An ultra-thin interposer utilizing 3D TSV technology
To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200 μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer. authors: W.C. Chiou, K.F. Yang, J.L. Yeh, S.H. Wang, Y.H. Liou, T.J. Wu, J.C. Lin, C.L. Huang, S.W. Lu, C.C. Hsieh, H.A. Teng, C.C. Chiu, H.B. Chang, T.S. Wei, Y.C. Lin, Y.H. Chen, H.J. Tu, H.D. Ko, T.H. Yu, J.P. Hung, P.H. Tsai, D.C. Yeh, W.C. Wu, A.J. Su, S.L. Chiu, S.Y. Hou, D.Y. Shih, Kim H. Chen, S.P. Jeng, C.H. Yu
Interconnect
Off-chip Interconnect
Silicon interposer, high-density fine-pitch fan-out RDL and bumpless bond are the three pillars of chip-to-chip interconnect on innovative advanced heterogeneous integration technologies (HIT). Each interconnect technology provides the best PPACC in their own domains of AI and 5G networks, and is tightly associated with a wafer-level heterogeneous integration technology, namely CoWoS, InFO and SoIC, respectively, in HPC and mobile application systems.
TSMC’s off-chip interconnect technologies continues to advance for better PPACC:
- Silicon interposer: high interconnect density, high specific capacitance density, and large reticle size for exascale HPC/AI
- Fan-out: high interconnect density and large reticle size in fan-out for cost and performance in HPC/network AI
- SoIC: high 3D interconnect density with ultra-low bonding latency for energy efficient computing systems
Note: PPACC: Power consumption, Performance, Area (form factor), Cost, Cycle time to market
