3D Multi-chip Integration with System on Integrated Chips (SoIC)
The electrical characterization of System on Integrated Chips (SoIC™), an innovative 3D heterogeneous integration technology manufactured in front-end of line with known-good-die is reported. Chiplets integration of devices including foundry leading edge 7nm FinFET technology with SoIC™ illustrates its advantages in high bandwidth density and high power efficiency, as compared with 2.5D and conventional 3D-IC with micro-bump/TSV. authors: C.C. Hu, M.F. Chen, W.C. Chiou, Doug C.H. Yu
Interconnect
Off-chip Interconnect
Silicon interposer, high-density fine-pitch fan-out RDL and bumpless bond are the three pillars of chip-to-chip interconnect on innovative advanced heterogeneous integration technologies (HIT). Each interconnect technology provides the best PPACC in their own domains of AI and 5G networks, and is tightly associated with a wafer-level heterogeneous integration technology, namely CoWoS, InFO and SoIC, respectively, in HPC and mobile application systems.
TSMC’s off-chip interconnect technologies continues to advance for better PPACC:
- Silicon interposer: high interconnect density, high specific capacitance density, and large reticle size for exascale HPC/AI
- Fan-out: high interconnect density and large reticle size in fan-out for cost and performance in HPC/network AI
- SoIC: high 3D interconnect density with ultra-low bonding latency for energy efficient computing systems
Note: PPACC: Power consumption, Performance, Area (form factor), Cost, Cycle time to market
