Computational Screening and Multiscale Simulation of Barrier-Free Contacts for 2D Semiconductor pFETs
Low-resistance p-type contacts to two-dimensional (2D) semiconductors remains a critical challenge towards the industrial application of 2D channel materials in advanced logic technology. To address this challenge, we computationally screen and identify designs for ultralow-resistance p-type contacts to 2D semiconductors such as WSe 2 by combining ab initio density-functional-theory (DFT) and quantum device simulations. Two new contact strategies, van der Waals metallic contact (such as 1H-NbS 2 ), and bulk semimetallic contact (such as Co 3 Sn 2 S 2 ), are identified as realistic pathways to achieving Schottky-barrier-free and low-contact-resistance p-type contacts for 2D semiconductor pFETs. Simulations of these new strategies suggest reduced metal-induced gap states, negligible Schottky barrier height and small contact resistance (down to ~20 Ω·μm). Preliminary experimental results in developing Co 3 Sn 2 S 2 as a new semimetal contact material are also demonstrated. authors: Ning Yang, Yuxuan Cosmi Lin, Chih-Piao Chuu, Saifur Rahman3, Tong Wu4, Ang-Sheng Chou, San-Lin Liew, Kohei Fujiwara, Hung-Yu Chen, Junya Ikeda, Atsushi Tsukazaki, Duen-Huei Hou, Wei-Yen Woon, Szuya Liao, Shengxi Huang, Xiaofeng Qian, Jing Guo, Iuliana Radu, H.-S. Philip Wong, Han Wang
Logic
Low Dimensional Material & Device
Transistor research team at TSMC is also exploring devices built on materials having intrinsically 2D or 1D carrier transport (low-dimensional transport). Transition metal dichalcogenides, graphene nanoribbons, and carbon nanotubes, among others, are being investigated theoretically and experimentally. TSMC research work is both internally conducted and/or in collaboration with our academic partners through joint development projects, or by active technical participation in leading research consortia or research institutes worldwide. Here we invite you to explore some of TSMC’s recent published work in these fields of active exploratory research.
The benefits of using 2D and 1D materials include high mobility at atomic thickness, excellent gate control, and potential applications for low-power and high-performance devices. Thus, transistor scaling may be extended. In a recent publication, we have successfully demonstrated the growth of wafer-scale h-Boron Nitride monolayer, which is able to efficiently protect the channel 2D semiconductors from process damages and the charge impurity scattering from adjacent dielectrics. 1D semiconducting carbon nanotubes, with processes compatible with the backend-of-line (BOEL) fabrication temperature (< 400 oC), are a potential component for achieving monolithic 3D ICs. The proof-of-concept monolithic integration of carbon nanotube transistors on our 28 nm CMOS technology wafers has also been demonstrated.
