Comprehensive Physics Based TCAD Model for 2D MX2 Channel Transistors
For the first time, a comprehensive TCAD model is developed to unambiguously extract key device parameters: contact resistance (R c ), channel mobility (μ CH ), Schottky barrier height (SBH), & D it from experimental data on back-gate (BG) transistors with MX 2 channel. The model is tested and validated against three different data sets with different contact metal, quality of channel, contact, and interfaces. Using model's output, we analyze the accuracy of R c and μ CH extracted by the TLM method and provide guidance on the limits of its applicability. Finally, the model is used to project contact requirements (SBH ~ 0eV, high doping density >2e13cm<sup>-2</sup> ) for performant, scaled transistors with 2D material channel in stacked nanosheet configuration. authors: D. Mahaveer Sathaiya
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Low Dimensional Material & Device
Transistor research team at TSMC is also exploring devices built on materials having intrinsically 2D or 1D carrier transport (low-dimensional transport). Transition metal dichalcogenides, graphene nanoribbons, and carbon nanotubes, among others, are being investigated theoretically and experimentally. TSMC research work is both internally conducted and/or in collaboration with our academic partners through joint development projects, or by active technical participation in leading research consortia or research institutes worldwide. Here we invite you to explore some of TSMC’s recent published work in these fields of active exploratory research.
The benefits of using 2D and 1D materials include high mobility at atomic thickness, excellent gate control, and potential applications for low-power and high-performance devices. Thus, transistor scaling may be extended. In a recent publication, we have successfully demonstrated the growth of wafer-scale h-Boron Nitride monolayer, which is able to efficiently protect the channel 2D semiconductors from process damages and the charge impurity scattering from adjacent dielectrics. 1D semiconducting carbon nanotubes, with processes compatible with the backend-of-line (BOEL) fabrication temperature (< 400 oC), are a potential component for achieving monolithic 3D ICs. The proof-of-concept monolithic integration of carbon nanotube transistors on our 28 nm CMOS technology wafers has also been demonstrated.
