Bilayer Alloy Contacts for High-Performance p-Type 2D Semiconductor Transistors
Notable progress has been reported for n-type contacts to two-dimensional (2D) materials, either through doping or through careful choice of contact metals. Here, we report on p-type contact engineering via substitutional doping and alloying. We tune the dopant concentration from lightly to heavily doped WSe2. We demonstrate that bilayer (2L) transition metal dichalcogenide (TMD) alloy can reach degenerate doping density for WSe2. The degenerate doping plays a critical role in lowering contact resistance (Rc) to metal. Extracted Rc is ~98 Ω·μm for a sheet resistance (Rsh) of 4.5 kΩ/sq, independent of the gate voltage (Vg). Pd/alloy contacts show superior thermal stability when compared to typical semimetal contacts (Bi and Sb). authors: Amin Azizi, Goutham Arutchelvan, Nathaniel Safron, Chih-Piao Chuu, Yangjin Lee, Mehmet Dogan, D. Mahaveer Sathaiya, H.-S. Philip Wong, Marvin Cohen, Alex Zettl3 and Iuliana P. Radu, Corporate Research, TSMC, San Jose, CA, USA, Corporate Research, TSMC, Hsinchu, Taiwan, University of California, Berkeley, CA, USA, TCADD, TSMC, Hsinchu, Taiwan
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Low Dimensional Material & Device
Transistor research team at TSMC is also exploring devices built on materials having intrinsically 2D or 1D carrier transport (low-dimensional transport). Transition metal dichalcogenides, graphene nanoribbons, and carbon nanotubes, among others, are being investigated theoretically and experimentally. TSMC research work is both internally conducted and/or in collaboration with our academic partners through joint development projects, or by active technical participation in leading research consortia or research institutes worldwide. Here we invite you to explore some of TSMC’s recent published work in these fields of active exploratory research.
The benefits of using 2D and 1D materials include high mobility at atomic thickness, excellent gate control, and potential applications for low-power and high-performance devices. Thus, transistor scaling may be extended. In a recent publication, we have successfully demonstrated the growth of wafer-scale h-Boron Nitride monolayer, which is able to efficiently protect the channel 2D semiconductors from process damages and the charge impurity scattering from adjacent dielectrics. 1D semiconducting carbon nanotubes, with processes compatible with the backend-of-line (BOEL) fabrication temperature (< 400 oC), are a potential component for achieving monolithic 3D ICs. The proof-of-concept monolithic integration of carbon nanotube transistors on our 28 nm CMOS technology wafers has also been demonstrated.
