Late News: 2nm Platform Technology featuring Energy-efficient Nanosheet Transistors and Interconnects co-optimized with 3DIC for AI, HPC and Mobile SoC Applications
A leading edge 2nm CMOS platform technology (N2) has been developed and engineered for energy-efficient compute in AI, mobile and HPC applications. This industry-leading N2 logic technology features energy-efficient gate-all-around nanosheet (NS) transistors, middle-of-line and backend-of-line interconnects with densest SRAM macro of ~38Mb/mm2. N2 delivers a full node benefit from previous 3nm node [2] in offering 15% speed gain or 30% power reduction with >1.15x chip density increase. N2 platform technology, equipped a new Cu scalable-RDL (sRDL), flat passivation and TSVs, co-optimizes holistically with 3DFabricTM technology enabling system integration/ scaling for AI/mobile/HPC product designs. N2 successfully met wafer-level reliability requirements and passed 1000hrs HTOL qual with high yielding 256Mb HC/HD SRAM (~>90%), and logic test chip (>3B gates) consisting of CPU/GPU/ SoC blocks. Currently in risk production, N2 platform technology is scheduled for mass production in 2H’25. N2P, 5% speed enhanced version of N2 with full GDS compatibility, targets to complete qualification in 2025 and mass production in 2026. authors: Geoffrey Yeap, S.S. Lin, H.L. Shang, H.C. Lin, Y.C. Peng, M. Wang, P.W. Wang, C.P. Lin, K.F. Yu, W-Y Lee, H.K. Chen, D.W. Lin, B.R. Yang, C.C. Yeh, C-T Chan, J.M. Kuo, C-M Liu, T.L. Lee, C.Y. Chang, R. Chen, P-H Huang, C.S. Hou, Y-K Lin, F.K. Yang, S. Fung, Ryan Chen, C.H. Lee, T.L. Lee, W. Chang, D-Y Lee, C-Y Ting, T. Chang, H-C Huang, H.J. Lin, C. Tseng, C.W. Chang, K.B. Huang, Y-C Lu, C-H Chen, C.O. Chui, K.W. Chen, M.H. Tsai, C.C. Chen, N. Wu, H.T. Chiang, X.M. Chen, S.H. Sun, J-T Tzeng, K. Wang, Y-C Peng, H.J. Liao, T. Chen, K-J Chen, Y-K Cheng, J. Chang, K. Hsieh, A. Cheng, K-C Chiang, C-W Tsai, H. Wang, J. Yeh, Y-M Chen, C-K Lin, J. Wu, M. Cao, L-S Juang, F. Lai, Y. Ku, S.M. Jang, L.C. Lu
Logic
Logic
TSMC has been at the forefront of advanced CMOS logic technologies for which dense transistors are one of the two essential building blocks, the other being dense interconnect stacks. The intrinsic computing capability of a given logic technology is directly related to the number of interconnected transistors and their switching speed under representative loads originating from both the transistor or gates being driven and the related interconnect resistive and capacitive circuit loads.
TSMC research and development is continuously exploring novel and scalable transistor concepts to ensure sustainable, cost-effective, leading-edge logic technology performance and energy efficiency. We invite you to explore some of TSMC research areas in transistor structure, high-mobility channel, and low-dimensional materials and devices.
