High-Performance Monolayer WSe2 p/n FETs via Antimony-Platinum Modulated Contact Technology towards 2D CMOS Electronics
Low resistance contact technology for 2D semiconductors is a key bottleneck for the practical application of 2D channel materials at advanced logic nodes. This work presents a novel Sb-Pt modulated contact technology which can alleviate the Fermi-level pinning effect and mediate the band alignment at the metal-2D semiconductor interface, leading to exceptional ohmic contacts for both p-type and n-type WSe 2 FETs (p/n FET). WSe 2 FETs with different Sb/Pt contact compositions, in combination with new oxide-based encapsulation/doping technologies, exhibits record low pFET contact resistance of 0.75kΩ∙μm among all reported monolayer (1L) 2D pFETs. The nFET contact resistance of 1.8kΩ∙μm is also the lowest among 1L WSe 2 nFETs. Both 1L WSe 2 pFET and nFET demonstrated remarkable on-state p/n current ∼150μA/μm at |V<sub>D</sub>|=1V, indicating the potential of WSe 2 for CMOS applications. A new version of the semi-automated dry transfer process for chemical vapor deposition (CVD) WSe 2 was also developed utilizing a novel Bi/PMMA/TRT support stack, offering low defect wrinkle-free WSe 2 transfer at wafer-scale. authors: Ang-Sheng Chou, Yu-Tung Lin, Yuxuan Cosmi Lin, Ching-Hao Hsu,, Ming-Yang Li, San-Lin Liew, Sui-An Chou, Hung-Yu Chen, Hsin-Yuan Chiu,, Po-Hsun Ho, Ming-Chun Hsu, Yu-Wei Hsu, Ning Yang, Wei-Yen Woon, Szuya Liao, Duen-Huei Hou, Chao-Hsin Chien, Wen-Hao Chang, Iuliana Radu, Chih-I Wu, H.-S. Philip Wong, Han Wang
Logic
Logic
TSMC has been at the forefront of advanced CMOS logic technologies for which dense transistors are one of the two essential building blocks, the other being dense interconnect stacks. The intrinsic computing capability of a given logic technology is directly related to the number of interconnected transistors and their switching speed under representative loads originating from both the transistor or gates being driven and the related interconnect resistive and capacitive circuit loads.
TSMC research and development is continuously exploring novel and scalable transistor concepts to ensure sustainable, cost-effective, leading-edge logic technology performance and energy efficiency. We invite you to explore some of TSMC research areas in transistor structure, high-mobility channel, and low-dimensional materials and devices.
