45nm high-k/metal-gate CMOS technology for GPU/NPU applications with highest PFET performance
Highest planar HK/MG PFET performance (I ON = 790 muA at I off = 100 nA, Vdd= 1 V and Lg= 33 nm) has been demonstrated with a gate-first dual-metal CMOS integrated process and proven by functional SRAM cell. Integrating modern stressors without IL re-growth and achieving band edge work function without increasing T INV are two major challenges for gate-first HK/MG processes. In this work, band-edge effective work function has been achieved without increasing T INV . Furthermore, with successful integration of stress techniques like SiGe-S/D, SMT and CESL, not only performance was improved by 30% but also no reliability degradation was observed. Finally, no degradation from decreasing poly-pitch also suggests its good scalability to next generations. authors: H.T. Huang, Y.C. Liu, Y.T. Hou, R. C-J Chen, C.H. Lee, Y.S. Chao, P.F. Hsu, C.L. Chen, W.H. Guo, W.C. Yang, T.H. Perng, J.J. Shen, Y. Yasuda, K. Goto, C.C. Chen, K.T. Huang, H. Chuang, C.H. Diaz, M.S. Liang
Logic
Logic
TSMC has been at the forefront of advanced CMOS logic technologies for which dense transistors are one of the two essential building blocks, the other being dense interconnect stacks. The intrinsic computing capability of a given logic technology is directly related to the number of interconnected transistors and their switching speed under representative loads originating from both the transistor or gates being driven and the related interconnect resistive and capacitive circuit loads.
TSMC research and development is continuously exploring novel and scalable transistor concepts to ensure sustainable, cost-effective, leading-edge logic technology performance and energy efficiency. We invite you to explore some of TSMC research areas in transistor structure, high-mobility channel, and low-dimensional materials and devices.
