Characterization of polysilicon resistors in sub-0.25 μm CMOS ULSI applications
The characteristics of polysilicon resistors in sub-0.25 μm CMOS ULSI applications have been studied. Based on the presented sub-0.25 μm CMOS borderless contact, both n/sup +/ and p/sup +/ polysilicon resistors with Ti- and Co-salicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate the essential parameters of polysilicon resistors including electrical delta W(/spl Delta/W), interface resistance R/sub interface/, and pure sheet resistance R/sub pure/. This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-0.25 μm CMOS technology. authors: Wen-Chau Liu, Kong-Beng Thei, Hung-Ming Chuang, Kun-Wei Lin, Chin-Chuan Cheng, Yen-Shih Ho, Chi-Wen Su, Shyh-Chyi Wong, Chih-Hsien Lin, C.H. Diaz
Logic
Logic
TSMC has been at the forefront of advanced CMOS logic technologies for which dense transistors are one of the two essential building blocks, the other being dense interconnect stacks. The intrinsic computing capability of a given logic technology is directly related to the number of interconnected transistors and their switching speed under representative loads originating from both the transistor or gates being driven and the related interconnect resistive and capacitive circuit loads.
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