0.18 μm CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications
This paper describes a leading-edge 0.18 /spl mu/m CMOS logic foundry technology. Very aggressive design rules and borderless contacts render a 4.4 /spl mu/m/sup 2/ embedded (synchronous cache) 6T SRAM cell demonstrated in a 1 Mb vehicle with very high yield. Robust dual-gate oxides were developed to support 1.5-2 V core logic as well as 3.3 V periphery (I/O) circuitry. Advanced modular core device technology using 32 /spl Aring/ oxides for 1.8-2 V operation and 27 /spl Aring/ oxides for 1.5-1.7 V applications support competitive high-performance (MPU/graphics) or low-standby power (mobile) applications. Transient-enhanced diffusion is effectively used in I/O devices to enhance hot-carrier lifetime. This is the first 0.18 /spl mu/m technology demonstrating a highly manufacturable 6 to 7 level low-k (HSQ)/AlCu interconnect system with tightest metal pitch (0.46 /spl mu/m M1 and 0.56 /spl mu/m at intermediate levels), as well as aggressive borderless and fully stacked vias without poisoning problems. AlCu/FSG and dual-damascene Cu/oxide interconnect options have also been proven with comparable SRAM yield to the AlCu/HSQ system. authors: C.H. Diaz, K.L. Young, J.H. Hsu, J.C.H. Lin, C.S. Hou, C.T. Lin, J.J. Liaw, C.C. Wu, C.W. Su, C.H. Wang, J.K. Ting, S.S. Yang, K.Y. Lee, S.Y. Wu, C.C. Tsai, H.J. Tao, S.M. Jang, S.L. Shue, H.C. Hsieh, Y.Y. Wang, C.C. Chen, S.C. Yang, S. Fu, S.Z. Chang, T.C. Lo, J.Y. Wu, J.S. Shy, C.W. Liu, S.H. Chen, B.L. Lin
Logic
Logic
TSMC has been at the forefront of advanced CMOS logic technologies for which dense transistors are one of the two essential building blocks, the other being dense interconnect stacks. The intrinsic computing capability of a given logic technology is directly related to the number of interconnected transistors and their switching speed under representative loads originating from both the transistor or gates being driven and the related interconnect resistive and capacitive circuit loads.
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