A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating
TSMC presents a UCIe-compliant die-to-die interface achieving 10.5Tb/s/mm beachfront density in 3nmtechnology. Over 64 lanes this paper demonstrates an aggregate eye width of 19ps (61% UI) and an eye height of560mV at 32Gb/s after lane deskew correction, with an energy efficiency of 0.6pJ/b. authors: Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Chih Chen, Wen-Hung Huang, Yu-Chi Chen, Yu-Jie Huang, Alan Drake, Chin Hua Wen, Paul Ranucci, Hsin-Hung Kuo, Aidong Yin, Shu-Chun Yang, Farsheed Mahmoudi, Han-Tzung Ke, Chao-Chieh Li, Nai-Chen Cheng, Jimmy Wang, Kevin Lin, Harry Liao, Jie-Ren Huang, Meng-Hsuan Wu, Kenny Cheng-Hsiang Hsieh, Nicholas Amatruda, William Polanco, David King, Todd Basso, Anwar Kashem, TSMC, Hsinchu, Taiwan, TSMC, San Jose, CA, TSMC, Austin, TX, TSMC, Nanjing, China, AMD, Austin, TX, AMD, San Jose, CA
Logic
Logic
TSMC has been at the forefront of advanced CMOS logic technologies for which dense transistors are one of the two essential building blocks, the other being dense interconnect stacks. The intrinsic computing capability of a given logic technology is directly related to the number of interconnected transistors and their switching speed under representative loads originating from both the transistor or gates being driven and the related interconnect resistive and capacitive circuit loads.
TSMC research and development is continuously exploring novel and scalable transistor concepts to ensure sustainable, cost-effective, leading-edge logic technology performance and energy efficiency. We invite you to explore some of TSMC research areas in transistor structure, high-mobility channel, and low-dimensional materials and devices.
