Channel stress modulation and pattern loading effect minimization of milli-second super anneal for sub-65nm high performance SiGe CMOS
In this paper, we present an advanced integration approach using milli-second anneal technique to enhance device performance. In addition to enhanced poly-silicon activation, the device gain resulted from channel stress modulation, and retarded dopant diffusion can be obtained through process optimization including rapid-thermal anneal (RTA), capping layer, and milli-second anneal. More than 15% NMOS performance gain is demonstrated without undergoing milli-second-anneal-induced pattern loading effect and re-crystallization defect. No obvious stress relaxation and driving current degradation are observed in epi-SiGe PMOS. Moreover, the performance gain is increased while lowering the RTA temperature, suggesting that our proposed approach may open an alternative pathway for 45nm technology node and beyond authors: Chien-Hao Chen, C.F Nieh, D.W. Lin, K.C. Ku, J.C. Sheu, M.H. Yu, L.T. Wang, H.H. Lin, H.H. Chang, T. Lee, K. Goto, C. Diaz, S.C. Chen, M.S. Liang
Logic
High Mobility Channel
Silicon has been the transistor channel material of choice throughout all CMOS technology generations up until our 7nm node. TSMC’s 5nm technology is the first advanced logic production technology featuring SiGe as the channel material for p-type FinFET.
TSMC is actively exploring alternative transistor channel materials as an additional degree of freedom in the design of high performance and low power devices. Silicon-germanium and germanium are examples of TSMC’s exploratory research work, which has been extensively published and in some cases recognized as highlights in international conferences.
