Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers
We demonstrate scaled, replacement gate high-k/metal gate p-channel Ge FinFETs integrated onto 300mm Si wafers for which the best device shows record peak g m, ext =2.7mS/μm (g m, int =3.3mS/μm), Q (≡g m, ext /SS sat ) = 32.4 and I on = 497μA/μm at I off = 100nA/μm, all at V ds = -0.5V. The high performance is a result of successful integration of <;110> oriented, highly scaled Ge fins on silicon substrates and of a low D it gate stack with capacitance equivalent thickness=8Å. This optimized gate stack supports the highest hole mobility ever reported at sub-10Å CET. Furthermore, Ge FinFETs in the present work outperform any other reported Ge devices by more than ~2.5× (g m /SS metric) and ~2× (I on /I off metric) at shortest gate lengths (down to 20nm) to the best of our knowledge. authors: B. Duriez, G. Vellianitis, M. J. H. van Dal, G. Doornbos, R. Oxland, K. K. Bhuwalka, M. Holland, Y. S. Chang, C. H. Hsieh, K. M. Yin, Y. C. See, M. Passlack, C. H. Diaz
Logic
High Mobility Channel
Silicon has been the transistor channel material of choice throughout all CMOS technology generations up until our 7nm node. TSMC’s 5nm technology is the first advanced logic production technology featuring SiGe as the channel material for p-type FinFET.
TSMC is actively exploring alternative transistor channel materials as an additional degree of freedom in the design of high performance and low power devices. Silicon-germanium and germanium are examples of TSMC’s exploratory research work, which has been extensively published and in some cases recognized as highlights in international conferences.
