Germanium n-Channel Planar FET and FinFET: Gate-Stack and Contact Optimization
We demonstrate Ge enhancement-mode nMOS FinFETs fabricated on 300-mm Si wafers, incorporating an optimized gate-stack (interface trap density D it below 2 × 10 11 eV -1 · cm -2 ), n + -doping (active doping concentration Nact exceeding 1 × 10 20 cm -3 ), and metallization (contact resistivity Pc below 2 × 10 -7 Ω · cm 2 ) modules. A new circular transmission line Pc extraction model that captures the parasitic metal resistance is proposed. At a supply voltage VDD of 0.5 V, 40-nm-gate-length FinFET devices achieved an ON-performance ION of 50 μA/μm at an OFF-state current IOFF of 100 nA/μm, a subthreshold swing S sat of 124 mV/decade, and a peak transconductance g m of 310 μS/μm. The same gate-stack and contacts were deployed on planar devices for comparison. Both FinFET and planar devices in this paper achieved the highest reported g m /S sat at VDD = 0.5 V to date and the shortest gate lengths for Ge nMOS enhancement-mode transistors. authors: Mark J. H. van Dal, Blandine Duriez, Georgios Vellianitis, Gerben Doornbos, Matthias Passlack, Yee-Chia Yeo, Carlos H. Diaz
Logic
High Mobility Channel
Silicon has been the transistor channel material of choice throughout all CMOS technology generations up until our 7nm node. TSMC’s 5nm technology is the first advanced logic production technology featuring SiGe as the channel material for p-type FinFET.
TSMC is actively exploring alternative transistor channel materials as an additional degree of freedom in the design of high performance and low power devices. Silicon-germanium and germanium are examples of TSMC’s exploratory research work, which has been extensively published and in some cases recognized as highlights in international conferences.
