AlxIn1−xAsySb1−y alloys lattice matched to InAs(1 0 0) grown by molecular beam epitaxyAlxIn1−xAsySb1−y quaternary alloys lattice-matched to InAs were successfully grown by molecular beam epitaxy (MBE) for use as buffer layers for substrate isolation in InAs channel devices. The use of In-containing quaternary buffer layers with 5% In was found to dramatically improve the heterointerface between the buffer and a surface InAs channel layer. The composition of these alloys and the extent of lattice matching were accurately determined by double crystal X-ray measurements. A simple model was used to estimate the variation of critical thickness with lattice mismatch for AlInAsSb epitaxially grown on an InAs substrate. Layers with high Al content and low As mole fraction were grown by modulated MBE technique which was found to significantly improve the surface morphology and the composition control of the alloys. In contrast, quaternary alloys with low Al content were grown by conventional MBE and had an rms roughness of less than 0.2 nm.
High-k dielectrics on (100) and (110) n-InAs: Physical and electrical characterizationsTwo high-k dielectric materials (Al2O3 and HfO2) were deposited on n-type (100) and (110) InAs surface orientations to investigate physical properties of the oxide/semiconductor interfaces and the interface trap density (Dit). X-ray photoelectron spectroscopy analyses (XPS) for native oxides of (100) and (110) as-grown n-InAs epi wafers show an increase in As-oxide on the (100) surface and an increase in InOx on the (110) surface. In addition, XPS analyses of high-k (Al2O3 and HfO2) on n-InAs epi show that the intrinsic native oxide difference between (100) and (110) epi surfaces were eliminated by applying conventional in-situ pre-treatment (TriMethyAluminium (TMA)) before the high-k deposition. The capacitance-voltage (C-V) characterization of HfO2 and Al2O3 MOSCAPs on both types of n-InAs surfaces shows very similar C-V curves. The interface trap density (Dit) profiles show Dit minima of 6.1 × 1012/6.5 × 1012 and 6.6 × 1012/7.3 × 1012 cm−2 eV−1 for Al2O3 and HfO2, respectively for (100) and (110) InAs surfaces. The similar interface trap density (Dit) on (100) and (110) surface orientation were observed, which is beneficial to future InAs FinFET device with both (100) and (110) surface channel orientations present.
Low interface trap density Al2O3/In0.53Ga0.47As MOS capacitor fabricated on MOCVD-grown InGaAs epitaxial layer on Si substrateA low interface trap density (Dit) Al2O3/In0.53Ga0.47As/Si MOS capacitor fabricated on an In0.53Ga0.47As heterostructure layer directly grown on a 300 mm on-axis Si(100) substrate by MOCVD with a very thin buffer layer is demonstrated. Compared with the MOS capacitors fabricated on the In0.53Ga0.47As layer grown on the lattice-matched InP substrate, the Al2O3/In0.53Ga0.47As MOS capacitors fabricated on the Si substrate exhibit excellent capacitance–voltage characteristics with a small frequency dispersion of approximately 2.5%/decade and a low interface trap density Dit close to 5.5 × 1011 cm−2 eV−1. The results indicate the potential of integrating high-mobility InGaAs-based materials on a 300 mm Si wafer for post-CMOS device application in the future.
Lifting the off-state bandgap limit in InAs channel metal-oxide-semiconductor heterostructures of nanometer dimensionsOne of the major challenges of high mobility complementary metal-oxide-semiconductor (CMOS) circuits is to meet off-current requirements of <100 pA/μm for low stand-by power (LSTP) operation due to the small bandgap (≤0.5 eV) of the channel material (bandgap limit). In this work, we present experimental proof that the bandgap limit can be overcome at nanometer dimensions leveraging the phenomenon of steady state deep depletion (SSDD). The occurrence of SSDD is investigated using high-k capacitors with 5 and 10 nm InAs channel on a n- or p-type doped lattice matched wide bandgap AlAsSb layer. Absence of charge carriers at the off-state band edge is observed for 5 nm InAs channel layers demonstrating occurrence of SSDD and lifting of the off-state bandgap limit providing a path to meet LSTP requirements for future high mobility CMOS. The authors would like to thank the Nano Lab at Lund University for manufacturing assistance and Y. C. Sun of TSMC for support.
Comparative study of high-k/GaSb interfaces for use in antimonide based MOSFETsElectrical interface quality of various high- k dielectrics on GaSb, including Al 2 O 3 , HfO 2 , LaAlO 3 , GdScO 3 , and HfO 2 /Ga 2 O 3 bilayer has been studied and compared with reference low (AlGaSb) and high D it (native oxide) interfaces using photoluminescence intensity measurements for the first time. Al 2 O 3 and HfO 2 /Ga 2 O 3 bilayer dielectrics are identified with the lowest interface recombination velocity (S=7×10 4 cm/s) and consequently D it integrated across essentially the entire bandgap. However, S for even the best identified high- k dielectrics is elevated by 140× over the low D it AlGaSb reference indicating the need of further improvements for envisioned use in Sb based MOSFETs.
Atomic ordering effect on SiGe electronic structureIn this paper, a realistic atomic model is used to study the atomic ordering effect on electronic structures of Si 0.5 Ge 0.5 . The hybrid density functional theory (DFT), HSE06, is chosen as the methodology. The calculated bandgap and effective masses of Si and Ge at various symmetry points are first validated by the reported experimental data and empirical pseudo-potential method (EPM) calculations. The study of two different Si 0.5 Ge 0.5 atomic configurations shows that the SiSi-GeGe case is more stable than SiGe-SiGe (RS2 structure). In addition, the electron effective masses of the former one are larger than those of the latter one, and those calculated by EPM with virtual crystal approximation (VCA). This large electron effective mass is attributed to the localized electron orbital of the lowest anti-bonding state in the SiSi-GeGe case which leads to a flat E-k curve. However, no obvious ordering effect on hole effective mass is found.
InAs Hole Inversion and Bandgap Interface State Density of 2x1011 cm-2 eV-1 at HfO2/InAs InterfacesHigh-k/InAs interfaces have been manufactured using InAs surface oxygen termination and low temperature atomic layer deposition of HfO2. Capacitance–voltage (C–V) curves revert to essentially classical shape revealing mobile carrier response in accumulation and depletion, hole inversion is observed, and predicted minority carrier response frequency in the hundred kHz range is experimentally confirmed; reference samples using conventional techniques show a trap dominated capacitance response. C–V curves have been fitted using advanced models including nonparabolicity and Fermi-Dirac distribution. For an equivalent oxide thickness of 1.3 nm, an interface state density Dit = 2.2 × 1011 cm−2 eV−1 has been obtained throughout the InAs bandgap. The authors would like to thank Y. C. Sun of TSMC and L. Samuelson of Lund University for their support.
InAs N-MOSFETs with record performance of Ion = 600 uA/um at Ioff = 100 nA/um (Vd = 0.5 V)Record setting III-V MOSFETs are reported. For the first time performance better than state-of-the-art HEMTs is demonstrated. For a MOSFET with 10 nm unstrained InAs surface channel and L g = 130 nm operating at 0.5 V, on-current as high as I on = 601 μA/μm (at fixed I off = 100 nA/μm) is achieved. This record performance is enabled by g m, ext = 2.72 mS/μm and S = 85 mV/dec, DIBL = 40 mV/V, resulting from breakthroughs in epitaxy and III-V/dielectric interface engineering. Measured mobility is 7100 cm 2 /V.s at n s = 6.7×10 12 cm -2 . Device simulations further elucidate the performance potential of III-V N-MOSFETs.
Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafersWe demonstrate scaled, replacement gate high-k/metal gate p-channel Ge FinFETs integrated onto 300mm Si wafers for which the best device shows record peak g m, ext =2.7mS/μm (g m, int =3.3mS/μm), Q (≡g m, ext /SS sat ) = 32.4 and I on = 497μA/μm at I off = 100nA/μm, all at V ds = -0.5V. The high performance is a result of successful integration of <;110> oriented, highly scaled Ge fins on silicon substrates and of a low D it gate stack with capacitance equivalent thickness=8Å. This optimized gate stack supports the highest hole mobility ever reported at sub-10Å CET. Furthermore, Ge FinFETs in the present work outperform any other reported Ge devices by more than ~2.5× (g m /SS metric) and ~2× (I on /I off metric) at shortest gate lengths (down to 20nm) to the best of our knowledge.
Electrical Characteristics of Al2O3/InSb MOSCAPs and the Effect of Postdeposition Annealing TemperaturesThe characteristics of Al2O3/InSb MOSCAPs processed with different postdeposition annealing (PDA) temperatures are investigated. X-ray photoelectron spectroscopy analysis shows a significant reduction of InSb-oxides after HCl plus trimethyl aluminum treatment and oxide deposition. Multifrequency capacitance-voltage (C–V) characteristics exhibit low-frequency and asymmetrical C–V behaviors, in which capacitance in the InSb conduction band side is lower than in the valence band side. The electrical properties of the MOSCAPs are sensitive to PDA temperature and degraded significantly at PDA temperature > 300 °C. This degradation is closely related to the diffusion of In, Sb into Al2O3 as indicated by transmission electron microscopy analyses.
High Mobility Channel
Silicon has been the transistor channel material of choice throughout all CMOS technology generations up until our 7nm node. TSMC’s 5nm technology is the first advanced logic production technology featuring SiGe as the channel material for p-type FinFET.
TSMC is actively exploring alternative transistor channel materials as an additional degree of freedom in the design of high performance and low power devices. Silicon-germanium and germanium are examples of TSMC’s exploratory research work, which has been extensively published and in some cases recognized as highlights in international conferences.