Student Contests

TSMC IC Layout Contest

Preliminary round: December 16, 2019 @ OIP Virtual Design Environment (VDE) in the Cloud

Final round: January 15, 2020 @ TSMC R&D Center in Hsinchu

TSMC held the first nationwide IC Layout Contest in Taiwan, as our pursuit to get the advanced layout technology valued and nurtured by universities. Through this contest we encouraged the young talents in Taiwan to join the field of IC design in advanced process technologies. IC layout is not only the key to bridge customers’ design innovation and TSMC’s process technologies, it also plays the critical role realizing the competitiveness of advanced technologies. Through Design & Technology Co-Optimization (DTCO), IC layout engineers work with technology development team hand-in-hand to define the architecture and the design rules for the new technology nodes and realize the Power, Performance, and Area (PPA) benefits through implementation.
From the onset of the IC Layout Contest, TSMC proactively conducted 15 seminars by visiting 14 universities in Taiwan. Through the face-to-face interactions with over 2,000 students and professors, we led them to see that layout is now playing a critical role in advanced technologies and the old thinking of it being a labor intensive work no longer applied. The result spoke for itself. We attracted 1,000 students and 150 advising professors signing up for the contest from 35 universities throughout Taiwan.
In order to deploy TSMC’s unique advanced technologies to this contest, TSMC collaborated with OIP Cloud Alliance partners, Cadence and Microsoft Azure, to build a groundbreaking Virtual Design Environment (VDE) exclusively for the contestants. VDE served as an innovative competition and learning platform in the Cloud that lifted the constraints of physical facilities, and ensured security protection of TSMC process technology.
In addition to the online training courses and hands-on practice sessions enabled by Cloud, we held three in-person contestant workshops in Hsinchu, Taipei and Tainan. Instructors from TSMC, Cadence and Microsoft jointly guided the contestants to familiarize themselves with IC layout technologies, EDA tools and Cloud environment. Even though the workshops were held in the weekends, the turnout was amazing with each session attracted hundreds of students to attend. The students seized the opportunity to pick up the learning through real-time interactions with the experts in the field. Instructors not only patiently responded to every IC layout question, but also shared their own industry experiences for students to get a better sense on what IC design at TSMC was all about.
After a total of 250 teams formed by 500 contestants concluded the preliminary contest in the Cloud, 17 teams were selected for the final contest. We brought them into TSMC’s R&D center in which the finalist workshop and the final contest were held. During the 10-hour marathon of the final contest, Dr. L.C. Lu, Senior Director of Design and Technology Platform of TSMC quietly showed up. The students and the event team felt the excitement of the unexpected arrival by the executive committee member.
The Award Ceremony was held in Morris Chang Lecture Hall at TSMC headquarter. The prizes of the winning teams were personally awarded by Dr. Cliff Hou, Senior Vice President of Technology Development at TSMC, and Dr. L.C. Lu, Senior Director of Design and Technology Platform at TSMC. John Ennis, Director of Worldwide Field Operations at Cadence, and Ken Sun, General Manager of Microsoft Taiwan Corp both attended the ceremony as the members of TSMC Cloud Alliance. Dr. Shyh-Jye Jerry Jou, Professor of Electronics Engineering Department at NCTU, who served as the chair of the judge panel also joint the event to witness this glorious moment belonging to all the young talents, along with numerous press covering the event.
While the semiconductor industry celebrated its 60th anniversary, the first TSMC IC Layout Contest jointly held with Cloud Alliance partners Cadence and Microsoft successfully led the students to understand the important role of IC layout in semiconductor innovations, and stimulated their interests in advanced technologies. We will continue our pursuits to strengthen the synergy between university and industry towards the common goal of nurturing next generation top-notch talents for the next 60 years of semiconductor industry.

TSMC Announces Winners of First IC Layout Contest
https://www.tsmc.com/tsmcdotcom/PRListingNewsArchivesAction.do?action=detail&newsid=THHIPGPGTH

TSMC Leads the Industry by Hosting the First "TSMC IC Layout Contest" in the Cloud
https://www.tsmc.com/csr/en/update/innovationAndService/caseStudy/22/index.html

Discover talented students in the IC industry!
https://www.eettaiwan.com/20191122NT11-The-First-TSMC-IC-Layout-Contest/

Everyone has potential to be outstanding here!
https://www.eettaiwan.com/20200122NT11-TSMC-Announces-Winners-of-First-IC-Layout-Contest/

2019/9

  • TSMC IC Layout Contest rollout
  • 15 technical lectures nationwide
  • Online layout skill and EDA software training courses officially launched

2019/10

  • VDE cloud-based IC design environment goes online

2019/11

  • Three workshops for contestants in Hsinchu, Taipei and Tainan

2019/12

  • Preliminary contest
  • Advanced training workshop for final teams

2020/1

  • Final contest and Award Ceremony

Executive Committee:

  • Dr. Cliff Hou, Senior Vice President of Technology Development, TSMC
  • Dr. L.C. Lu, TSMC Fellow/Senior Director of Design and Technology Platform, TSMC

Host: Design and Technology Platform (DTP), TSMC

  • Layout Design Engineering Team:
    L.J. Tyan
    Benson Chiang
    Don C.L. Chen
    Hui-Zhong Zhuang
    Philip Wang
    Pin-Dai Sue
    Mao-Wei Chiu
    Evan Liu
    Hao-Jie Zhan
  • OIP and Layout Contest Marketing Team:
    Willy Chen
    Vivian Jiang
    Shu-Yi Ying
    Yi-Wen Chang

Judges

  • L.J. Tyan, Deputy Director of Layout Design Engineering Division, TSMC
  • Willy Chen, Deputy Director of Design Infrastructure Management Division, TSMC
  • Benson Chiang, Manager of Layout Design Engineering Division, TSMC ◆ Mike Fang, Director of R&D, Cadence
  • Shyh-Jye Jerry Jou, Professor of Electronics Engineering Department of National Chiao Tung University

Sponsors:

  • Cadence
  • Microsoft Azure

Pre-contest University Roadshow:

  • 2019/9/17 National Chiao Tung University
  • 2019/9/18 Yuan Ze University
  • 2019/9/18 National Central University
  • 2019/9/19 National Cheng Kung University
  • 2019/9/24 National Kaohsiung University of Science and Technology
  • 2019/9/25 National Tsing Hua University
  • 2019/9/27 National Kaohsiung Normal University
  • 2019/9/27 National Sun Yat-sen University
  • 2019/9/27 National Yunlin University of Science and Technology
  • 2019/10/2 National University of Kaohsiung
  • 2019/10/2 National Taipei University of Technology
  • 2019/10/4 National Chung Hsing University
  • 2019/10/9 National Taiwan University
  • 2019/10/14 National Taiwan University of Science and Technology

First Place: NT$200,000 cash prize and trophy

Second Place: NT$100,000 cash prize and trophy

Third Place: NT$80,000 cash prize and trophy

Honorable mention: NT$20,000 cash prize and trophy

Outstanding Digital Layout: NT$10,000 cash prize and trophy

Outstanding Analog Layout: NT$10,000 cash prize and trophy

Completion Award: NT$10,000 cash prize and trophy


The first place, the second place and the third place teams are awarded with priority status for selection to TSMC summer internship opportunities.

2019/11, Three workshops for contestants in Hsinchu, Taipei and Tainan

Despite the sunny weather during weekend holidays that were suitable for outdoor activities, contestants eagerly participated the workshops to gain first-hand knowledge on IC layout skills from industry experts.

2019/12, Advanced training workshop for final teams

2020/1, Award Ceremony

Participated students agreesively took notes on the learning from the industry experts that they do not learn from schools, and proactively solicited advices from the instructors during the intermissions.