TSMC @ Conferences
Invited: The Overview of Current Interconnect Technology Challenges and Future Opportunities
As dimension shrinks managing line resistance and capacitance become a pressing issue for back-end-of line interconnect, as both increase dramatically at small pitches. Reducing resistance or capacitance by pushing the limit of current technology often come at a cost. Therefore, employing new materials and processes are necessary to mitigate the RC delay while maintaining the yield and reliability of the interconnect. This paper will discuss the challenges facing current interconnect and review the technologies that are intended to extend it. In additional, various novel materials will be discussed for their potential application in future interconnect.
Invited: Next-Generation Design and Technology Co-optimization (DTCO) of System on Integrated Chip (SoIC) for Mobile and HPC Applications
This paper demonstrates the next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications, where the SoIC technology was proposed to integrate multi-chips with different functionality and technology into a single SoC chip. The new DTCO includes overall die partitioning, die integration, and interconnect. These methodologies can be used for improving time-to-market and trade-off between performance and cost. In this paper, two prototypes of stacking CPU and memory dies are demonstrated with 15% performance gain and 30% average point-to-point distance reduction.
Pinning-Free Side Contact Monolayer MoS2 FET
One-dimensional contact (so-called edge contact) to monolayer 2D materials has been proposed for ultimate transistor scaling but reported on-state currents are much lower than those from top contact devices. Experiments in this work reveal that the fabrication processes for metal MoS2 contact strongly affect the electrical characteristics such as Schottky barrier height. Using in-situ 2D etching and metal deposition, we obtained Fermi-level pinning-free Ni-MoS2 edge contact transistor devices. Moreover, it reaches the highest on-state current among those TMDs edge contact devices reported in literatures and comparable to top-contact ones. First-principles calculation reveals the evolution of local electronic structure from strong metallization at the edge contact “interline” (1D equivalent of “interface”) to semiconductor in the channel region. The short length (<3 nm) of metal-semiconductor transition and the low-dimensionality nature of the edge contact eliminate Fermi level pining. The pinning free edge contact formed through in-situ process enables 2D based high performance FET.
A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process
The proliferation of AI-enabled edge devices and autonomous vehicles has driven the desire for higher compute power in micro-controllers (MCUs). That motivated the migration of some MCUs from more matured nodes to more advanced logic platforms of 16nm FinFET processes and below. STT-MRAM is a promising alternative solution to the traditional eFlash, with much lower mask adder count and good compatibility to the logic baseline. In this paper, we present the design and silicon characterization results of a reflow-capable 8Mb STT-MRAM macro in 16nm FinFET Logic CMOS process, with read access time of 9ns from -40C to 125C. Endurance of 100K cycles and reflow tolerance is demonstrated. Together with the high performance logic transistors in 16nm FinFET process, they make a promising candidate for high performance micro-controller applications.
Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length
Extending Moore’s law beyond the limits of Silicon CMOS technology motivates our study of low-dimensional semiconducting materials. A promising candidate transistor channel material is 1-dimensional semiconducting carbon nanotube (CNT), a single-walled cylinder of sp2-bonded carbon atoms roughly 1 nm in diameter, which is projected to deliver improvements to transistor density, energy efficiency, and speed compared to sub-5 nm node Silicon transistors. However, over the past two decades researchers have struggled to demonstrate a thin and high capacitance gate oxide on top of CNT due to the inert sp2-bonded carbon surface that is incompatible with conventional atomic layer deposition (ALD) of high-k oxides. This work introduces an optimized interfacial layer dielectric (ILX) which nucleates a continuous film with thickness sub-0.5 nm on CNT and allows high-k oxide to be grown by conventional ALD on top. Enabled by ILX, top-gate CNT transistors are demonstrated down to 15 nm gate length that display nearly ideal 65 mV/dec sub-VT slope, negligible hysteresis, and DIBL as low as 20 mV/V. The scaling limit of this method is investigated, showing as thin as 0.35 nm interfacial dielectric with 2.5 nm high-k ALD film achieves the sub-1 pA/CNT leakage target at 0.7V supply voltage. TCAD modeling predicts the demonstrated oxide is capable of meeting the stringent targets of high-performance CNFETs with 10 nm gate length and 4 nm spacing between CNTs.
Reliability of Ultrathin High-κ Dielectrics on Chemical-vapor Deposited 2D Semiconductors
Zhihao Yu, Hongkai Ning, Chao-Ching Cheng, Weisheng Li, Lei Liu, Wangqing Meng, Zhongzhong Luo,Taotao Li, Songhua Cai, Peng Wang, Wen-Hao Chang, Chao-Hsin Chien, Yi Shi, Yong Xu, Lain-Jong Li, Xinran Wang
2D semiconductors are considered to be one of the most promising channel materials to extend transistor scaling. However, the integration of ultra-thin dielectrics on 2D semiconductors has been challenging, and the reliability has not been investigated to date. Here, using monolayer 3,4,9,10-perylenetetracarboxylic dianhydride (PTCDA) molecules as interface layer, we realize EOT as low as 1.7 nm on large-area monolayer CVD MoS2. The reliability of ultrathin high-κ dielectric on 2D semiconductors is systematically studied for the first time. The median breakdown (BD) field of HfO2/PTCDA stack is over 8.42 MV/cm, which is two times that of HfO2/Si under the same EOT. Through TDDB we project that the gate dielectric can work reliably for 10 years under EBD = 6.5 MV/cm, which shows 85% improvement than HfO2/Si. The BD current increase rate in our gate stack is several orders of magnitude smaller than HfO2/Si. The excellent reliability suggests that molecular interfacial layer is a promising dielectric technology for 2D electronics.
Switchable NAND and NOR Logic Computing in Single Triple-Gate Monolayer MoS2 n-FET
Yun-Yan Chung, Chao-Ching Cheng, Bo-Kai Kang, Wei-Chen Chueh, Shih-Yun Wang, Chen-Han Chou, Terry Y.T. Hung, Shin-Yuan Wang, Wen-Hao Chang, Lain-Jong Li, Chao-Hsin Chien
We propose a novel triple-gated single transistor comprising monolayer MoS2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS2 n-FET and switchable easily through top-gate bias setting (VLOW / VHIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications.